Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
Buffer
Number of Channels
4
Schmitt Trigger Input
No
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
12.6ns
Maximum Operating Supply Voltage
3.6 V
Dimensions
5.1 x 4.5 x 0.95mm
Maximum Operating Temperature
+125 °C
Length
5.1mm
Height
0.95mm
Width
4.5mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
6.512 OMR
0.204 OMR Each (In a Pack of 32) (ex VAT)
6.838 OMR
0.214 OMR Each (In a Pack of 32) (inc. VAT)
Standard
32
6.512 OMR
0.204 OMR Each (In a Pack of 32) (ex VAT)
6.838 OMR
0.214 OMR Each (In a Pack of 32) (inc. VAT)
Stock information temporarily unavailable.
Standard
32
Stock information temporarily unavailable.
Quantity | Unit price | Per Pack |
---|---|---|
32 - 288 | 0.204 OMR | 6.512 OMR |
320 - 768 | 0.182 OMR | 5.808 OMR |
800 - 3168 | 0.165 OMR | 5.280 OMR |
3200+ | 0.148 OMR | 4.752 OMR |
Technical Document
Specifications
Brand
NexperiaLogic Family
LVC
Logic Function
Buffer
Number of Channels
4
Schmitt Trigger Input
No
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
14
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
12.6ns
Maximum Operating Supply Voltage
3.6 V
Dimensions
5.1 x 4.5 x 0.95mm
Maximum Operating Temperature
+125 °C
Length
5.1mm
Height
0.95mm
Width
4.5mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS