Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
8bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
20
Dimensions
12.8 x 7.52 x 2.35mm
Height
2.35mm
Length
12.8mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Maximum Operating Supply Voltage
3.6 V
Width
7.52mm
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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0.360 OMR
Each (In a Tube of 25) (ex VAT)
0.378 OMR
Each (In a Tube of 25) (inc VAT)
25
0.360 OMR
Each (In a Tube of 25) (ex VAT)
0.378 OMR
Each (In a Tube of 25) (inc VAT)
25
Buy in bulk
quantity | Unit price | Per Tube |
---|---|---|
25 - 100 | 0.360 OMR | 9.000 OMR |
125 - 475 | 0.330 OMR | 8.250 OMR |
500 - 1225 | 0.300 OMR | 7.500 OMR |
1250+ | 0.280 OMR | 7.000 OMR |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
8bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
20
Dimensions
12.8 x 7.52 x 2.35mm
Height
2.35mm
Length
12.8mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Maximum Operating Supply Voltage
3.6 V
Width
7.52mm
Minimum Operating Temperature
-40 °C
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22