Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Monostable Multivibrator
Number of Elements per Chip
1
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Minimum Pulse Width
2.5 ns
Maximum Quiescent Current
20µA
Mounting Type
Surface Mount
Package Type
SM
Pin Count
8
Dimensions
3.15 x 2.9 x 1.2mm
Height
1.2mm
Length
3.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Maximum Operating Supply Voltage
5.5 V
Width
2.9mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
1.890 OMR
0.126 OMR Each (In a Pack of 15) (ex VAT)
1.984 OMR
0.132 OMR Each (In a Pack of 15) (inc. VAT)
Standard
15
1.890 OMR
0.126 OMR Each (In a Pack of 15) (ex VAT)
1.984 OMR
0.132 OMR Each (In a Pack of 15) (inc. VAT)
Standard
15
Stock information temporarily unavailable.
Please check again later.
quantity | Unit price | Per Pack |
---|---|---|
15 - 60 | 0.126 OMR | 1.890 OMR |
75 - 135 | 0.121 OMR | 1.811 OMR |
150 - 360 | 0.116 OMR | 1.732 OMR |
375 - 735 | 0.110 OMR | 1.654 OMR |
750+ | 0.105 OMR | 1.575 OMR |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Monostable Multivibrator
Number of Elements per Chip
1
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Minimum Pulse Width
2.5 ns
Maximum Quiescent Current
20µA
Mounting Type
Surface Mount
Package Type
SM
Pin Count
8
Dimensions
3.15 x 2.9 x 1.2mm
Height
1.2mm
Length
3.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Maximum Operating Supply Voltage
5.5 V
Width
2.9mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22