Technical Document
Specifications
Brand
NexperiaLogic Function
NAND
Mounting Type
Surface Mount
Number Of Elements
4
Number of Inputs per Gate
2
Schmitt Trigger Input
Yes
Package Type
SOIC
Pin Count
14
Logic Family
LVC
Input Type
Schmitt Trigger
Maximum Operating Supply Voltage
3.6 V
Maximum High Level Output Current
-24mA
Minimum Operating Supply Voltage
1.2 V
Maximum Low Level Output Current
24mA
Minimum Operating Temperature
-40 °C
Height
1.45mm
Dimensions
8.75 x 4 x 1.45mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
8.75mm
Width
4mm
Country of Origin
Thailand
Product details
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
6.050 OMR
0.302 OMR Each (In a Pack of 20) (ex VAT)
6.352 OMR
0.317 OMR Each (In a Pack of 20) (inc. VAT)
20
6.050 OMR
0.302 OMR Each (In a Pack of 20) (ex VAT)
6.352 OMR
0.317 OMR Each (In a Pack of 20) (inc. VAT)
20
Stock information temporarily unavailable.
Please check again later.
| Quantity | Unit price | Per Pack |
|---|---|---|
| 20 - 20 | 0.302 OMR | 6.050 OMR |
| 40 - 80 | 0.231 OMR | 4.620 OMR |
| 100 - 180 | 0.226 OMR | 4.510 OMR |
| 200 - 380 | 0.220 OMR | 4.400 OMR |
| 400+ | 0.220 OMR | 4.400 OMR |
Technical Document
Specifications
Brand
NexperiaLogic Function
NAND
Mounting Type
Surface Mount
Number Of Elements
4
Number of Inputs per Gate
2
Schmitt Trigger Input
Yes
Package Type
SOIC
Pin Count
14
Logic Family
LVC
Input Type
Schmitt Trigger
Maximum Operating Supply Voltage
3.6 V
Maximum High Level Output Current
-24mA
Minimum Operating Supply Voltage
1.2 V
Maximum Low Level Output Current
24mA
Minimum Operating Temperature
-40 °C
Height
1.45mm
Dimensions
8.75 x 4 x 1.45mm
Propagation Delay Test Condition
50pF
Maximum Operating Temperature
+125 °C
Length
8.75mm
Width
4mm
Country of Origin
Thailand
Product details
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS


