Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Number of Channels per Chip
1
IC Type
Buffer & Line Driver IC
Input Type
Single Ended
Output Type
Open Drain
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
5.5 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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0.335 OMR
Each (On a Reel of 250) (ex VAT)
0.352 OMR
Each (On a Reel of 250) (inc VAT)
250
0.335 OMR
Each (On a Reel of 250) (ex VAT)
0.352 OMR
Each (On a Reel of 250) (inc VAT)
250
Buy in bulk
quantity | Unit price | Per Reel |
---|---|---|
250 - 250 | 0.335 OMR | 83.750 OMR |
500 - 1000 | 0.270 OMR | 67.500 OMR |
1250 - 2250 | 0.250 OMR | 62.500 OMR |
2500+ | 0.235 OMR | 58.750 OMR |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Driver
Number of Channels per Chip
1
IC Type
Buffer & Line Driver IC
Input Type
Single Ended
Output Type
Open Drain
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.2 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
5.5 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22