Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
1bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
6
Dimensions
2.15 x 1.4 x 1mm
Height
1mm
Length
2.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Maximum Operating Supply Voltage
5.5 V
Width
1.4mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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0.110 OMR
Each (Supplied as a Tape) (ex VAT)
0.116 OMR
Each (Supplied as a Tape) (inc VAT)
20
0.110 OMR
Each (Supplied as a Tape) (ex VAT)
0.116 OMR
Each (Supplied as a Tape) (inc VAT)
20
Buy in bulk
quantity | Unit price | Per Tape |
---|---|---|
20 - 80 | 0.110 OMR | 2.200 OMR |
100 - 180 | 0.075 OMR | 1.500 OMR |
200 - 980 | 0.060 OMR | 1.200 OMR |
1000 - 2980 | 0.040 OMR | 0.800 OMR |
3000+ | 0.040 OMR | 0.800 OMR |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Latch Mode
Transparent
Latching Element
D Type
Number of Bits
1bit
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
6
Dimensions
2.15 x 1.4 x 1mm
Height
1mm
Length
2.15mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Maximum Operating Supply Voltage
5.5 V
Width
1.4mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22