Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5.4 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Width
1.25mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2mm
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
105.875 OMR
0.424 OMR Each (On a Reel of 250) (ex VAT)
111.169 OMR
0.445 OMR Each (On a Reel of 250) (inc. VAT)
250
105.875 OMR
0.424 OMR Each (On a Reel of 250) (ex VAT)
111.169 OMR
0.445 OMR Each (On a Reel of 250) (inc. VAT)
250
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Please check again later.
quantity | Unit price | Per Reel |
---|---|---|
250 - 250 | 0.424 OMR | 105.875 OMR |
500 - 1000 | 0.341 OMR | 85.250 OMR |
1250+ | 0.319 OMR | 79.750 OMR |
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
2
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
6
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5.4 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Height
0.9mm
Width
1.25mm
Minimum Operating Temperature
-40 °C
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2mm
Product details
74LVC2G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS