Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-74A
Pin Count
5
Logic Family
LVC
Dimensions
3.1 x 1.7 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
1.7mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
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0.060 OMR
Each (Supplied on a Reel) (ex VAT)
0.063 OMR
Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
100
0.060 OMR
Each (Supplied on a Reel) (ex VAT)
0.063 OMR
Each (Supplied on a Reel) (inc. VAT)
Production pack (Reel)
100
Buy in bulk
quantity | Unit price | Per Reel |
---|---|---|
100 - 100 | 0.060 OMR | 6.000 OMR |
200 - 400 | 0.060 OMR | 6.000 OMR |
500 - 900 | 0.055 OMR | 5.500 OMR |
1000 - 1900 | 0.035 OMR | 3.500 OMR |
2000+ | 0.035 OMR | 3.500 OMR |
Technical Document
Specifications
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-74A
Pin Count
5
Logic Family
LVC
Dimensions
3.1 x 1.7 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
1.7mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS